Multi-Cavity Package Having Single Metal Flange

ABSTRACT

A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a dielectric material attached to the first main surface of the single metal flange. The dielectric material includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The dielectric material also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The dielectric material also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.

RELATED APPLICATIONS

This application is a continuation of prior U.S. application Ser. No.16/589,624, filed 1 Oct. 2019, which is a continuation of prior U.S.application Ser. No. 14/673,928, filed 31 Mar. 2015, and issued as U.S.patent Ser. No. 10/468,399 on 5 Nov. 2019, the entire disclosure of eachof which is incorporated by reference herein.

TECHNICAL FIELD

The present application relates to power semiconductor packages, inparticular power semiconductor packages with multiple semiconductordies.

BACKGROUND

In highly space-constrained systems, multi-stage power amplifier designsare typically implemented using integrated circuit (IC) technology whichhas several limitations that make its use unattractive in many cases.For example, the design time and process flow to make an IC is very longwhich in-turn increases the overall product turnaround time. Also, theinter-stage match between different amplifier stages is provided on thechip (die) with IC technology and because of the proximity of bond-wiresand resulting coupling mechanisms, an IC has a very high tendency to beunstable and hence unusable. Furthermore, IC processing involvesexpensive semiconductor fabrication processes which increase the designand development cost to make such products. In addition, conventionalmulti-stage power amplifier IC designs provide at most about 30 dB gain.Any higher gain increases the risk of power amplifier IC instability andhence renders the IC unusable.

SUMMARY

According to an embodiment of a multi-cavity package, the multi-cavitypackage comprises a single metal flange having first and second opposingmain surfaces, a circuit board attached to the first main surface of thesingle metal flange, the circuit board having a plurality of openingswhich expose different regions of the first main surface of the singlemetal flange, and a plurality of semiconductor dies each of which isdisposed in one of the openings in the circuit board and attached to thefirst main surface of the single metal flange. The circuit boardcomprises a plurality of metal traces for electrically interconnectingthe semiconductor dies to form a circuit.

According to an embodiment of a method of manufacturing a multi-cavitypackage, the method comprises: providing a single metal flange havingfirst and second opposing main surfaces; attaching a circuit board tothe first main surface of the single metal flange, the circuit boardhaving a plurality of openings which expose different regions of thefirst main surface of the single metal flange; placing a plurality ofsemiconductor dies in the openings of the circuit board; attaching thesemiconductor dies to the first main surface of the single metal flange;and electrically interconnecting the semiconductor dies through aplurality of metal traces of the circuit board to form a circuit.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts. The features of the various illustrated embodiments can becombined unless they exclude each other. Embodiments are depicted in thedrawings and are detailed in the description which follows.

FIG. 1 illustrates a top side perspective view of an embodiment of amulti-cavity package.

FIG. 2 illustrates a top side perspective view of another embodiment ofa multi-cavity package.

FIG. 3 illustrates a top side perspective view of yet another embodimentof a multi-cavity package.

FIGS. 4A through 4D illustrate an embodiment of a method ofmanufacturing a multi-cavity package.

FIG. 5 illustrates a side perspective view of an embodiment of a singlemetal flange and circuit board configuration for a multi-cavity package.

DETAILED DESCRIPTION

Described next are embodiments of a multi-stage power amplifier circuitprovided on a single metal flange. The input of the final RF powertransistor die (chip) is matched to the output of the driver RF powertransistor die using circuit board technology such as PCB (printedcircuit board) or components such as inductors, capacitors, resistorsetc. for implementing the inter-stage match. The single metal flange canhave two or more power amplifier stages attached to the flange. Such aconfiguration enables higher gain in a smaller area e.g. more than 35 dBgain (for two stages) while reducing amplifier instability concerns. Fora higher number of stages, the gain provided can be around 45 dB or evengreater.

The embodiments described herein enable manufacture of a packagedDoherty amplifier circuit device with main and peaking amplifier diesattached to a single metal flange along with a Doherty combiner on theoutput side of the package. Such a configuration saves space and reducesdesign complexity for the user base-station design. Such a design can beapplied to other applications of transmitters as well.

In each case, the multi-stage package design embodiments describedherein enable high gain devices using a multi-cavity package where thedielectric is comprised out of PCB or similar dielectric material suchas Teflon, ceramic, LTCC, polyimide, etc. and which simplifies userdesign by integrating RF power amplifier functionality at the packagelevel, such as output matching for Doherty amplifier design, inputmatch, driver+input+output match, etc. The leads/terminals of themulti-stage power amplifier package described herein can be soldereddown onto the application board without requiring additional connectorsfor the signal path. The single metal flange can be soldered or screweddown depending on the application manufacturing practice. Themulti-stage power amplifier package is an open cavity package design,and a lid can be provided for protecting the interconnects and circuitcomponents.

FIG. 1 illustrates a top side perspective view of an embodiment of amulti-cavity package 100. The multi-cavity package 100 comprises asingle metal flange 102 having first and second opposing main surfaces104, 106 and a circuit board 108 such as a PCB attached to the firstmain surface 104 of the single metal flange 102. The single metal flange102 can comprise Cu, CPC (copper, copper-molybdenum, copper laminatestructure) CuW, or any similar alloy, etc.

The circuit board 108 can be attached to the first main surface 104 ofthe single metal flange 102 by and standard circuit board attach processsuch as gluing, soldering, sintering, brazing, etc. The circuit board108 mechanically supports and electrically connects electroniccomponents using conductive traces (also referred to as tracks), padsand other features etched from metal (e.g. copper) sheets laminated ontoa non-conductive substrate 110. The circuit board 108 can be singlesided (one metal layer), double sided (two metal layers) or multi-layer.Conductors on different layers are connected with plated-through holescalled vias. The circuit board 108 can contain components such ascapacitors, resistors, active devices, etc. embedded in thenon-conductive substrate 110. The circuit board 108 also has a pluralityof openings 112 which expose different regions 114, 116, 118 of thefirst main surface 104 of the single metal flange 102.

The multi-cavity package 100 further comprises a plurality ofsemiconductor dies 120-142, each of which is disposed in one of theopenings 112 in the circuit board 108 and attached to the first mainsurface 104 of the single metal flange 102 via a die attach material(out of view) such as solder, diffusion soldering, sintering, adhesive,etc. For example, the semiconductor dies 120-142 can be attached to thesingle metal flange 102 using soft solder, a eutectic die attachmaterial such as AuSi or AuSn, an organic adhesive, etc. Metal traces144, 146, 148 of the circuit board 108 electrically interconnect thesemiconductor dies 120-142 and the external electrical terminals to forma circuit. For example, wire bonds 150 can electrically connectrespective ones of the metal traces 144, 146, 148 to different terminalsof the semiconductor dies 120-142 to form the desired circuit.

Some or all of the semiconductor dies 120-142 can be activesemiconductor dies such as power transistor dies, power diode dies, etc.and/or contain passive components such as capacitors, inductors andresistors. Each active semiconductor die 124, 132, 140 can be a lateralor vertical device or some other form of transistor used foramplification.

In the case of a vertical device, the current flow direction is betweenthe bottom and top sides of the die. The transistor die may have threeterminals. For example, the bottom side of the die can be a powerterminal such as the source of a power MOSFET (metal oxide semiconductorfield effect transistor), or collector of an IGBT (insulated gatebipolar transistor), or anode/cathode of a power diode. The powerterminal is attached to the region 114/116/118 of the single metalflange 102 which is exposed by the corresponding opening 112 in thecircuit board 108 e.g. by diffusion soldering. The gate anddrain/emitter terminals in the case of a transistor die or thecathode/anode terminal in the case of a power diode die are disposed atthe opposite side of the die i.e. the side facing away from the singlemetal flange 102.

In the case of a lateral device, the current flow direction ishorizontal and the bottom side of the die is not active. The respectivedrain or collector terminal of such a device has interconnects on thetop side, as well. The circuit board 108 would then still connect thedrain and gate terminal or equivalent control terminals on top of thesemiconductor die. The top-side terminals of the semiconductor dies120-142 can be attached to the to-side terminals of an adjacent die orto one of the circuit board metal traces 144, 146, 148 e.g. through wirebonds 150.

One or more of the semiconductor dies 120-142 disposed in the openings112 formed in the circuit board 108 can be a passive semiconductor diedevoid of active devices such as a capacitor, resistor or an inductordie. In the case of a capacitor die 120, 122, 126, 128, 130, 134, 136,138, 142, one of the capacitor terminals is at the bottom side of thecapacitor die and attached to the single metal flange 102. The othercapacitor terminal is disposed at the opposite side of the capacitor diei.e. the side facing away from the single metal flange 102.

The multi-cavity package 100 can be enclosed with an optional lid sothat the package is an open-cavity package. The multi-cavity package 100allows for a simplified product and development process by usingmultiple openings (cut-outs) 112 in the circuit board 108 such that thecircuit board 108 provides openings 112 through which passive and/oractive components are attached to the single metal flange 102. Forexample in the case of two openings 112 in the circuit board 108, thecircuit board 108 provides two cavities to die attach active/passivecomponents to the single metal flange 102. As such, a two-stage highgain amplifier device can be provided on the same metal flange 102 bydisposing the drive stage die in one of the circuit board openings 112and the final stage die in the other opening 112. For such a two stageamplifier design, instead of developing the inter-stage match using asemiconductor technology such as silicon, the multi-cavity package 100described herein enables the inter-stage match design using transmissionlines formed from the circuit board metal traces 144, 146 148 andpassive components mounted in the cavity or on the board and thatresults in significantly reduced development time. Designing circuitboard based inter-stage match topologies reduces the cost of the overallproduct development process because expensive silicon processing is notrequired. Furthermore, the multi-cavity package 100 allows customizedsolutions for different applications by having more cavities/openings112 in the circuit board 108. For example, a phase shifter and/or anattenuator can be formed from one or more of the circuit board metaltraces 144, 146 148. Such an implementation enables a dual-pathindependently controlled driver and Doherty power amplifier device.

According to the multi-cavity package embodiment shown in FIG. 1, one ofthe semiconductor dies 124 is a driver stage die of a Doherty amplifiercircuit, a second one of the semiconductor dies 132 is a main (orcarrier) amplifier die of the Doherty amplifier circuit, and a third oneof the semiconductor dies 140 is a peaking amplifier die of the Dohertyamplifier circuit. Passive semiconductor dies 120, 122, 126, 128, 130,134, 136, 138, 142 which form part of various match networks of theDoherty amplifier circuit such as input and output match networks alsocan be placed in the circuit board openings 112 and attached to thesingle metal flange 102 as shown in FIG. 1.

One of the circuit board metal traces 146 forms an inter-stage matchbetween the output of the driver stage die 124 and the input of the mainamplifier die 132 and the input of the peaking amplifier die 140. Asecond one of the circuit board metal traces 148 forms a Dohertycombiner electrically connected to the output of the main amplifier die132 and the output of the peaking amplifier die 140. A third one of thecircuit board metal traces 144 electrically connects the externalterminal to the input of the driver stage die 124. The third metal trace144 can be shaped to form a phase shifter, attenuator, etc. at the inputof the driver stage die 124. As such, the multi-cavity package 100 shownin FIG. 1 has the main and peaking devices (separated with a groundshield for better isolation) on a single metal flange 102 along with aDoherty combiner 148 on the package.

The two signals output by the Doherty amplifiers 132, 140 are out ofphase by 90 degrees. The Doherty combiner 148 can include a λ/4 (quarterwave) transmission line 152 connected to the output of the peakingamplifier 140. By doing so, the Doherty amplifier outputs are broughtback into phase and reactively combined. At this point, the two signalsin parallel create a Z0/2 impedance where Z0 corresponds to the loadimpedance. The Doherty combiner 148 can further include a λ/4 (quarterwave) transformer 154 for stepping this impedance to Z0. In a fifty ohmsystem, the transformer 154 would be 35.35 ohms. The Doherty combiner148 can be implemented as printed transmission lines on the circuitboard. The transformer 154 could be other impedance depending upon theimpedance required at the terminal 160.

By implementing the Doherty combiner on the circuit board 108, theimpact of package parasitics on amplifier performance is reduced. Also,interface related losses between the multi-cavity package 100 and themain system board are reduced as are inconsistencies in high volumeproduction environment, all while guarding against low yield impact. Assuch, the overall circuit board size can be reduced and the overallamplifier design simplified.

The circuit board 108 can have at least one lateral extension 156, 158which overhangs the single metal flange 102 to form an interface forattaching the multi-cavity package 100 to another structure such asanother PCB, metal flange, etc. According to the embodiment shown inFIG. 1, the circuit board 108 has opposing first and second lateralextensions 156, 158 each of which overhangs the single metal flange 102to form two opposing interfaces for attaching the multi-cavity package100 to one or more structures at opposing ends of the multi-cavitypackage 100. The output metal trace 148 of the circuit board 108 canextend onto the lateral extension 158 at the output side of themulti-cavity package 100 and/or the input metal trace 144 of the circuitboard 108 can extend onto the lateral extension 156 at the input side ofthe multi-cavity package 100. The output metal trace 148 provides anoutput electrical pathway for the Doherty amplifier circuit, and theinput metal trace 144 provides an input electrical pathway for thecircuit. Each metal trace 144, 148 which extends onto one of the lateralextensions 156, 158 can have a plurality of plated-through holes calledvias 160 which extend through the corresponding lateral extension 156,158. The vias 160 provide input/output points of connection to the mainsystem board (not shown). For example, the main system board can besoldered to the corresponding vias 160 of the multi-cavity package 100.The connection can also be provided by soldering the trace or using asingle (large) filled via.

FIG. 2 illustrates a top side perspective view of another embodiment ofa multi-cavity package 200. The multi-cavity package embodiment shown inFIG. 2 is similar to the embodiment shown in FIG. 1. Different, however,a first one of the semiconductor dies is a driver stage die 202 of apower amplifier circuit and a second one of the semiconductor dies is apower or final stage die 204 of the power amplifier circuit. One of themetal traces 206 of the circuit board 108 forms an inter-stage matchbetween the output of the driver stage die 202 and the input of thepower stage die 204. A second one of the circuit board metal traces 208is electrically connected to the output of the power stage die 204, anda third one of the circuit board metal traces 210 is electricallyconnected to the input of the driver stage die 202. In the case of an RFpower amplifier circuit, the second metal trace 208 can be shaped in theform of an antenna which transmits an RF signal output by the powerstage die 204. One or more of the semiconductor dies disposed in theopenings 112 formed in the circuit board 108 can be passivesemiconductor dies 212, 214, 216, 218 such as capacitor dies aspreviously described herein, which form part of the power amplifiercircuit.

FIG. 3 illustrates a top side perspective view of yet another embodimentof a multi-cavity package 300. The multi-cavity package embodiment shownin FIG. 3 is similar to the embodiment shown in FIG. 2. Different,however, at least some of the semiconductor dies have a surface mountconfiguration in that these dies can be mounted or placed directly ontometal traces 206, 208, 210, 220, 222, 224, 226 of the circuit board 108.For example, at least some of the passive components that make up thecircuit such as the capacitor dies 212, 214, 216, 218 can besurface-mounted directly onto the metal traces 206, 208, 210, 220, 222,224, 226 of the circuit board 108 instead of the single metal flange102.

FIGS. 4A through 4D illustrate an embodiment of a method ofmanufacturing a multi-cavity package.

In FIG. 4A, a single metal flange 400 is provided which has first andsecond opposing main surfaces 402, 404. The single metal flange 400 cancomprise Cu, CPC (copper, copper-molybendum, copper laminate structure)CuW, or any other suitable alloy, etc.

In FIG. 4B, a circuit board 406 such as a PCB is attached to the firstmain surface 402 of the single metal flange 404 e.g. by gluing,soldering, sintering, brazing, etc. The circuit board 406 has aplurality of openings (cutouts) 408 which expose different regions 410,412 of the first main surface 402 of the single metal flange 400. Thecircuit board 406 also has conductive traces (tracks) 414, 416, 418etched from metal (e.g. copper) sheets laminated onto a non-conductivesubstrate 420. The circuit board 406 also can have at least one lateralextension 422, 424 which overhangs the single metal flange 400 to forman attachment interface. The input and/or output metal traces 414, 418of the circuit board 406 can extend onto the corresponding lateralextension 422, 424 and can each have a plurality of plated-through holes(vias) 426 or a single (large) via which extend through thecorresponding lateral extension 422, 424 to provide input/output pointsof connection to the main system board (not shown) as previouslydescribed herein. Alternatively or in addition, the connection can beprovided by soldering the lateral extensions 422, 424 directly to themain system board.

In FIG. 4C, a plurality of semiconductor dies 428-438 are placed in theopenings 408 in the circuit board 406. Some or all of the semiconductordies 428-438 are vertical and/or lateral active semiconductor dies suchas power transistor dies, power diode dies, etc. and the remainder ofthe die(s) are passive dies such as capacitor dies as previouslydescribed herein.

In FIG. 4D, the semiconductor dies 428-438 are attached to the firstmain surface 402 of the single metal flange 400 via a die attachmaterial such as solder, diffusion soldering, sintering, adhesive, etc.Also, the semiconductor dies 428-438 are electrically interconnectedthrough the metal traces 414, 416, 418 of the circuit board and wirebonds 440 or other types of electrical conductors to form a circuit suchas a Doherty amplifier circuit, a power amplifier circuit, etc.

FIG. 5 illustrates a side perspective view of an embodiment of a singlemetal flange and circuit board configuration for a multi-cavity package.The semiconductor dies and wire bond connections typically provided aspart of the package are omitted in FIG. 5 for ease of illustration.Similar to the multi-cavity package embodiments previously describedherein, a circuit board 500 is attached to a single metal flange 502.The circuit board 500 has at least one lateral extension 504, 506 whichoverhangs a respective edge face 508, 510 of the single metal flange 502to form an attachment interface for the package. The circuit board 500has input and/or output metal traces 512, 514 which extend onto thecorresponding lateral extension 504, 506. The input and/or output metaltraces 512, 514 further extend onto respective edge faces 516, 518 andoptionally onto respective bottom faces 520, 522 of the correspondinglateral extension 504, 506 to provide input/output points of connectionto a main system board (not shown). For example, each lateral extension504, 506 of the circuit board 500 can be soldered to the main systemboard along the edge face 516/518 and optionally along the bottom face520/522 of the corresponding input/output metal trace 512, 514.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

It is to be understood that the features of the various embodimentsdescribed herein may be combined with each other, unless specificallynoted otherwise.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A multi-cavity package, comprising: a singlemetal flange having first and second opposing main surfaces; adielectric material attached to the first main surface of the singlemetal flange, the dielectric material comprising: a first surface facingthe single metal flange; a second surface facing away from the firstsurface; and a plurality of openings exposing respective regions of thefirst main surface of the single metal flange.
 2. The multi-cavitypackage of claim 1, further comprising a metal trace disposed on thesecond surface of the dielectric material and configured to provide aninput or output electrical pathway to a semiconductor die when thesemiconductor die is disposed in one of the openings and is attached tothe main surface of the single metal flange.
 3. The multi-cavity packageof claim 2, wherein the metal trace further extends onto an edge surfaceof the dielectric material, the edge surface being adjacent to the firstand second surfaces.
 4. The multi-cavity package of claim 3, wherein themetal trace further extends from the edge surface onto the first surfaceof the dielectric material.
 5. The multi-cavity package of claim 2,further comprising the semiconductor die and a further semiconductor diedisposed in respective ones of the openings and attached to the firstmain surface of the single metal flange.
 6. The multi-cavity package ofclaim 5, wherein at least one of the semiconductor dies is an amplifierdie.
 7. The multi-cavity package of claim 5, wherein the dielectricmaterial supports a further metal trace configured to electricallyinterconnect the semiconductor dies to form a circuit.
 8. Themulti-cavity package of claim 7, wherein the metal trace and furthermetal trace are comprised in a single layer disposed on the secondsurface of the dielectric material.
 9. The multi-cavity package of claim5, wherein at least one of the semiconductor dies is a transistor diehaving a first terminal attached to the single metal flange through theopening in the dielectric material in which that semiconductor die isdisposed, and a second terminal and a third terminal at a side of thetransistor die opposite the first terminal.
 10. The multi-cavity packageof claim 9, wherein the second terminal of the transistor die iselectrically connected to a first one of the metal traces and the thirdterminal of the transistor die is electrically connected to a second oneof the metal traces.
 11. The multi-cavity package of claim 5, wherein atleast one of the semiconductor dies is a passive semiconductor diedevoid of active devices.
 12. The multi-cavity package of claim 5,wherein: a first one of the semiconductor dies is a driver stage die ofa Doherty amplifier circuit; a second one of the semiconductor dies is amain amplifier die of the Doherty amplifier circuit; the multi-cavitypackage further comprises a peaking amplifier die of the Dohertyamplifier circuit, the peaking amplifier die disposed in a correspondingone of the openings in the dielectric material and attached to the firstmain surface of the single metal flange; an output of the driver stagedie and an input of the main amplifier die and an input of the peakingamplifier die are electrically interconnected via an inter-stage match;and an output of the main amplifier die and an output of the peakingamplifier die are electrically connected to a Doherty combiner.
 13. Themulti-cavity package of claim 12, further comprising a phase shifter oran attenuator at the input of the driver stage die.
 14. The multi-cavitypackage of claim 5, wherein: a first one of the semiconductor dies is adriver stage die of a power amplifier circuit; a second one of thesemiconductor dies is a power stage die of the power amplifier circuit;the multi-cavity package further comprises an inter-stage match betweenan output of the driver stage die and an input of the power stage die;and a second one of the metal traces is electrically connected to anoutput of the power stage die.
 15. The multi-cavity package of claim 14,wherein the power amplifier circuit is an RF power amplifier circuit andthe multi-cavity package further comprises an antenna of the RF poweramplifier circuit electrically connected to an output of the power stagedie.
 16. The multi-cavity package of claim 5, further comprising one ormore additional semiconductor dies attached to a surface of thedielectric material facing away from the single metal flange andelectrically connected to one or more of the semiconductor dies disposedin the openings of the dielectric material.
 17. The multi-cavity packageof claim 1, wherein the dielectric material further comprises a lateralextension that overhangs the single metal flange.
 18. The multi-cavitypackage of claim 17, wherein the lateral extension forms an interfacefor attaching the multi-cavity package to another structure.
 19. Themulti-cavity package of claim 17, further comprising at least one viathat extends through the lateral extension.
 20. The multi-cavity packageof claim 17, wherein the dielectric material: further comprises afurther lateral extension overhanging the single metal flange and awayfrom the lateral extension; and supports a circuit comprising anelectrical input pathway extending onto the lateral extension, and anelectrical output pathway extending onto the further lateral extension.21. A method of manufacturing a multi-cavity package, the methodcomprising: providing a single metal flange having first and secondopposing main surfaces; attaching a dielectric material to the firstmain surface of the single metal flange, such that: a first surface ofthe dielectric material faces the single metal flange; a second surfaceof the dielectric material faces away from the single metal flange; aplurality of openings in the dielectric material expose differentregions of the first main surface of the single metal flange; and alateral extension of the dielectric material overhangs the single metalflange.